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Tech Circuits
Manufacturing Capabilities
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Capability Standard Advanced Leading
Edge		 Emerging
PTH Through Hole Cu Plating Aspect Ratio6 to 18 to 110 to 1> 10 to 1
Z Axis Depth Drilled Cu Plating Aspect Ratio.5.751 to 1> 1 to 1
Drilled Hole Size Minimum - Vias.0138" dia..0098" dia..0079" dia..0059" dia.
Outer Layer Via Land (Pad) Size Minimum.026" dia..020" dia..018" dia..014" dia.
Inner Layer Via Land (Pad) Size Minimum.026" dia..020" dia..018" dia..014" dia.
Plane Layer Via Relief (Antipad) Minimum.038" dia..030" dia..026" dia..022" dia.
Buried Via Land (Pad) Size Minimum.026" dia..020" dia..018" dia..014" dia.
Buried Via Hole Size - Sequential Lamination.0135" dia..010" dia..008" dia..006" dia.
Microvia Cu Plating Aspect Ratio.5 to 1.75 to 11 to 1> 1 to 1
Microvia Laser Ablated.006" dia..004" dia..003" dia..002" dia.
Microvia Pad Size.010" dia..008" dia..006" dia.< .006" dia.
Minimum Line Width.005".004".003".003"
Minimum Line to Line Spacing.005".004".004".003"
Drill Hole to Conductor up to 10 Layers.010".008".006".006"
Drill Hole to Conductor 12+ Layers.012".010".008".008"
Layer to Layer Registration Tolerance +/-.005".004".003".002"
Maximum PCB Thickness.250".250".250".250"
Minimum Dielectric Thickness.005".003".0025".001"
PCB Edge to Conductor.020".015".010"< .010"
Electrical Test Minimum Component Pitch.010".005".004".003"
Soldermask Clearance per Side.004".003".002".001"
Line to SMT Land Minimum Space.006".005".004".003"
Average Layer Countup to 12 Layers20 Layers30 Layers30+ Layers
Average Panel Size18"x24" [457x610 mm] Usable 16.5x22.5" [419x572 mm]
Bow & Twist0.75%0.75%0.50%0.50%
Plated Through Holes Tolerance +/-.003".0025".002".002"
Impedance Tolerance +/-10%5%5%3%
Copper Pour to Feature Spacing (Outer).010".008".006".006"
Copper Pour to Feature Spacing (Inner).008".006".005".004"
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